Horizontal gate all around and finfet device isolation

ABSTRACT

Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims benefit to U.S. Provisional Patent ApplicationNo. 62/159,715, filed May 11, 2015 and to U.S. Provisional PatentApplication No. 62/265,260, filed Dec. 9, 2015, both of which are herebyincorporated herein by reference in their entirety.

BACKGROUND

1. Field

Embodiments of the present disclosure generally relate to semiconductordevices. More specifically, embodiments described herein relate tohorizontal gate all around device structures and fin field effecttransistor device structures. Further embodiments relate to methods forforming horizontal gate all around device structures and fin fieldeffect transistor device structures.

2. Description of the Related Art

As the feature sizes of transistor devices continue to shrink to achievegreater circuit density and higher performance, there is a need toimprove transistor device structure to improve electrostatic couplingand reduce negative effects such as parasitic capacitance and off-stateleakage. Examples of transistor device structures include a planarstructure, a fin field effect transistor (FinFET) structure, and ahorizontal gate-all-around (hGAA) structure. The hGAA device structureincludes several lattice matched channels suspended in a stackedconfiguration and connected by source/drain regions.

However, challenges associated with hGAA structures include theexistence of a parasitic device at the bottom of the stacked latticematched channels. FinFET structures, which may exhibit differentarchitectures from hGAA structures, also suffer from parasitic leakageand capacitance. Conventional approaches to mitigate the effects of theparasitic device include the implantation of dopants into the parasiticdevice to suppress leakage of the device. However, a dosage of thedopants required to suppress the leakage may hinder epitaxial growth ofdevice structures on the parasitic device. The dopants may deleteriouslydiffuse into channels of the device structures during subsequentprocessing operations, which may result an undesirable increase indevice variability. In addition, implantation may not adequately reduceparasitic capacitance. Another conventional approach utilizes thermaloxidation of a highly doped parasitic device. However, thermal oxidationprocesses generally require temperatures beyond the thermal budgets ofthe stacked lattice matched channels.

Accordingly, what is needed in the art are improved methods for formingFinFET and hGAA device structures.

SUMMARY

In one embodiment, a device structure is provided. The device structureincludes a substrate having a superlattice structure formed thereon. Thesuperlattice structure includes a silicon material layer, a firstsilicon germanium material layer comprising between about 20% and about40% germanium, and a second silicon germanium material layer comprisingbetween about 50% and about 80% germanium. The silicon material layer,the first silicon germanium material layer, and the second silicongermanium material layer are disposed in a stacked arrangement.

In another embodiment, a device structure is provided. The devicestructure includes a superlattice structure which includes a siliconmaterial layer, a first silicon germanium material layer comprisingbetween about 20% and about 40% germanium, and a second silicongermanium material layer comprising between about 50% and about 80%germanium. The silicon material layer, the first silicon germaniummaterial layer, and the second silicon germanium material layer aredisposed in a stacked arrangement.

In yet another embodiment, a device structure is provided. The devicestructure includes a substrate having a superlattice structure formedthereon. The superlattice structure includes one or more siliconmaterial layers, one or more first silicon germanium material layerscomprising between about 20% and about 40% germanium, and a buried oxidelayer. The silicon material layers, the silicon germanium materiallayers, and the buried oxide layer are disposed in a stackedarrangement.

In yet another embodiment, a device structure is provided. The devicestructure includes a superlattice which includes one or more siliconmaterial layers, one or more first silicon germanium material layerscomprising between about 20% and about 40% germanium, and a buried oxidelayer. The silicon material layers, the silicon germanium materiallayers, and the buried oxide layer are disposed in a stackedarrangement.

In yet another embodiment, a device structure is provided. The devicestructure includes a substrate having a superlattice structure formedthereon. The superlattice structure includes one or more siliconmaterial layers, one or more silicon germanium material layerscomprising between about 20% and about 40% germanium, and a buried oxidelayer. The silicon material layers, the silicon germanium materiallayers, and the buried oxide layer are disposed in a stackedarrangement. Source/drain regions are formed on the substrate and ametal gate structure is formed over the superlattice structure.

In yet another embodiment, a device structure is provided. The devicestructure includes a substrate and a buried oxide layer disposed on andin contact with the substrate. A silicon layer or silicon germaniumlayer comprising between about 20% and about 40% germanium is disposedon the buried oxide layer. Source/drain regions are formed on thesubstrate and a metal gate structure is formed over the silicon layer orsilicon germanium layer.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the presentdisclosure can be understood in detail, a more particular description ofthe disclosure, briefly summarized above, may be had by reference toembodiments, some of which are illustrated in the appended drawings. Itis to be noted, however, that the appended drawings illustrate onlyexemplary embodiments and are therefore not to be considered limiting ofits scope, may admit to other equally effective embodiments.

FIG. 1 illustrates operations of a method for forming a buried oxidematerial in a device structure.

FIG. 2 illustrates a schematic, cross-sectional view of a portion of asubstrate having a superlattice structure formed thereon.

FIG. 3 illustrates a schematic, cross-sectional view of a portion of thesubstrate and superlattice structure of FIG. 2 after patterning,etching, and buried oxide layer formation processes are performed.

FIG. 4 illustrates a schematic, cross-sectional view of a portion of thesubstrate and superlattice structure of FIG. 3 after a liner formationprocess is performed.

FIG. 5 illustrates a schematic, cross-sectional view of a portion of thesubstrate and superlattice structure of FIG. 4 after a shallow trenchisolation (STI) process is performed.

FIG. 6 illustrates a schematic, cross-sectional view of a portion of thesubstrate and superlattice structure of FIG. 5 after an annealingprocess is performed.

FIG. 7 illustrates a schematic, cross-sectional view of a portion of thesubstrate and superlattice structure of FIG. 6 after an STI recessprocess is performed.

FIG. 8 illustrates a schematic, cross-sectional view of a portion of thesubstrate and superlattice structure of FIG. 7 after formation of adummy gate structure.

FIG. 9 illustrates a schematic, cross-sectional view of FIG. 8 rotated90° depicting source and drain regions formed on the substrate adjacentthe superlattice structure.

FIG. 10 illustrates a cluster tool which may be utilized in accordancewith one or more of the embodiments described herein.

FIG. 11 illustrates a schematic, cross-sectional view of a devicestructure which may be formed and/or implemented in a device accordingto embodiments described herein.

FIG. 12 illustrates a schematic, cross-sectional view of a deviceincorporating the device structure of FIG. 11.

To facilitate understanding, identical reference numerals have beenused, where possible, to designate identical elements that are common tothe figures. It is contemplated that elements and features of oneembodiment may be beneficially incorporated in other embodiments withoutfurther recitation.

DETAILED DESCRIPTION

Embodiments described herein generally relate to methods and devicestructures for horizontal gate all around (hGAA) isolation and fin fieldeffect transistor (FinFET) isolation. A superlattice structurecomprising different materials arranged in an alternatingly stackedformation may be formed on a substrate. In one embodiment, at least oneof the layers of the superlattice structure are oxidized to form aburied oxide layer adjacent the substrate.

In one example, the superlattice structure includes one or more siliconcontaining material layers and one or more silicon germanium (SiGe)containing material layers disposed in an alternating stackedarrangement. At least one of the SiGe layers has a higher germaniumcontent when compared to other SiGe layers in the superlatticestructure. The higher germanium content SiGe layer is oxidized to form aburied oxide layer to provide for improved device isolation in an hGAAor FinFET architecture. As a result, a substantially defect free stackedchannel structure which can provide a geometric benefit in the currentdensity per square micrometer of surface area on a substrate may beachieved. Accordingly, circuit density may be increased, parasiticleakage and capacitance may be reduced, and power consumption of thedevice may be reduced.

FIG. 1 illustrates operations of a method 100 for forming a buried oxidematerial in an hGAA or FinFET structure. The method 100 may be part of amulti-operation fabrication process of a semiconductor device, forexample, an hGAA or FinFET device. At operation 110, a superlatticestructure is formed on a substrate. The term superlattice, as utilizedherein, generally refers to a stack of material layers which are closelylattice matched materials, but are sufficiently different in compositionthat selective removal processes can be performed on the superlatticestructure. More generally, the composition of various material layers inthe stack may be unique to one or more of the materials layers in thestack. In one example, the superlattice structure includes one or morelayers of a silicon containing material and a silicon germaniumcontaining material. In one embodiment, the superlattice structureincludes a first material layer and a second material layer. In anotherembodiment, the superlattice structure includes a first material layer,a second material layer, and a third material layer. In this embodiment,the second material layer and the third material layer are formed fromthe same compound material, but may have different material properties.

At operation 120, the superlattice structure is patterned and etched. Atoperation 130, at least one of the first material layer, the secondmaterial layer, or the third material layer are oxidized to form aburied oxide (BOX) layer. In one example, the second material layer andthe third material layer are oxidized. In another example, the thirdmaterial layer is oxidized.

At operation 140, a liner material is formed on sidewalls of thesuperlattice structure. In one embodiment, the liner material isdeposited, for example, by a chemical vapor deposition, an atomic layerdeposition, or epitaxial deposition process. In another embodiment, theliner material is formed (i.e. grown) by suitable processes, such asthermal oxidation or thermal nitridation processes. The liner materialis generally configured to repair portions of the superlattice structurewhich may be damaged during previous etching processes. The linermaterial may also prevent or reduce oxidation of material layers in thesuperlattice structure during subsequent processing operations.

In one embodiment, the liner material is an oxide material, a nitridematerial, or an oxynitride material. For example, the liner material maybe a SiO₂ material, a SiN material, or a SiON material. In otherembodiments, the liner material contains carbon and/or boron. Forexample, the liner material may be a SiCN material, a SiOCN material, aSiBN material, a SiOBN material, and/or a SiOBCN material. In anotherembodiment, the liner material is a phosphosilicate glass (PSG), aborosilicate glass (BSG), or doped glass material. It is contemplatedthat the various aforementioned liner materials may be doped in certainembodiments.

At operation 150, a shallow trench isolation (STI) material is depositedon the substrate. In one embodiment, the STI material is an oxidematerial, such as SiO₂ or the like. Generally, the oxide material isformed over and around the superlattice structure. In one embodiment,the oxide material is deposited by a flowable chemical vapor deposition(CVD) process.

At operation 160, an annealing process is performed on the substrate. Inone embodiment, the annealing process includes a steam annealingprocess. In another embodiment, the annealing process includes a steamannealing process and a dry annealing process. In yet anotherembodiment, the annealing process includes a dry annealing process (i.e.no steam). Generally, the annealing process provides for improveddensification of the STI material which may improve isolation offeatures formed on the substrate.

At operation 170, an STI recess process is performed. Generally, the STImaterial is etched to expose a portion of the superlattice. In oneembodiment, the STI material is recessed such that the STI material isco-planar with the BOX layer. STI planarization may also be performedprior to the STI recess process. A more detailed description of themethod 100 is provided in the description of FIGS. 2-7, which illustratevarious stages of fabrication of a semiconductor device.

FIG. 2 illustrates a schematic, cross-sectional view of a portion of asubstrate 202 having a superlattice structure 200 formed thereon. In oneembodiment, the substrate 202 is a bulk semiconductor substrate. Theterm bulk semiconductor substrate refers to a substrate in which theentirety of the substrate is comprised of a semiconductor material. Thebulk semiconductor substrate includes any suitable semiconductingmaterial and/or combinations of semiconducting materials for forming asemiconductor structure. For example, the semiconducting layer maycomprise one or more materials such as crystalline silicon (e.g.,Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium,doped or undoped polysilicon, doped or undoped silicon substrates,patterned or non-patterned substrates, doped silicon, germanium, galliumarsenide, or other suitable semiconducting materials. In oneembodiments, the semiconductor material is silicon. In otherembodiments, the semiconductor material is a doped material, such asn-doped silicon (n-Si), or p-doped silicon (p-Si).

The superlattice structure 200 includes a plurality of first layers 204and a corresponding plurality of second layers 206 alternatinglyarranged in a plurality of stacked pairs. In one embodiment, theplurality of first layers 204 are formed from a silicon containingmaterial. In one embodiment, the plurality of second layers 206 areformed from at least a silicon containing material and a germaniumcontaining material. Accordingly, the first layers 204 and the secondlayers 206 are different materials. In some embodiments, the pluralityof first layers 204 and corresponding plurality of second layers 206 arelattice matched materials with a sufficient difference in compositionsuch that selective layer removal or selective oxidation cansubsequently be performed.

In certain embodiments, the plurality of first layers 204 include GroupIV materials, such as silicon. The plurality of second layers 206include Group IV materials, such as silicon germanium (SiGe). In otherembodiments, the plurality of first layers 204 and the plurality ofsecond layers 206 include various III-V materials, such asindium-phosphorus (InP) and indium-gallium-phosphorus (InGaP),respectively. In some embodiments, the plurality of first layers 204 andthe plurality of second layers 206 are multiple pairs of lattice matchedmaterials. In some embodiments, the plurality of first layers 204 andcorresponding plurality of second layers 206 may be any number oflattice matched material pairs suitable for forming the superlatticestructure 200. For example, the plurality of first layers 204 andcorresponding plurality of second layers 206 include between about 2 toabout 5 pairs of lattice matched materials.

Material layer 210 and material layer 208 are included the in theplurality of second layers in one embodiment. Alternatively, materiallayer 208 may be considered a third material layer. Material layers 210and 208 are formed from the same material as the plurality of secondlayers 206, such as silicon germanium. However, it is contemplated thatthe compositional profile of the material layers 210 and 208 may differin molar ratio of Si:Ge.

In one example, the plurality of first layers 204 and the material layer210 have a silicon:germanium molar ratio of between about 1:1 and about5:1. In one embodiment, the silicon germanium material of the pluralityof first layers 204 and the material layer 210 has a germanium contentof between about 10% and about 50%, such as between about 20% and about40%. The silicon content is between about 30% and about 90%, such asbetween about 50% and about 80%, for example, about 70%. Alternatively,the plurality of first layers 204 may be formed from a pure siliconmaterial. In another example, the material layer 208 has asilicon:germanium molar ratio of between about 1:1 and about 1:5. In oneembodiment, the silicon germanium material of the material layer 208 hasa germanium content of between about 20% and about 100%, such as betweenabout 50% and about 80%. The silicon content is between about 0% andabout 80%, such as between about 20% and about 40%.

The plurality of first layers 204, the plurality of second layers 206,and the material layers 210, 208 are deposited using an epitaxialchemical vapor deposition process. Suitable precursors for forming theplurality of first layers 204, the plurality of second layers 206, andthe material layers 210, 208 include SiH₄ and GeH₄, among others. Incertain embodiments, the plurality of first layers 204 and the pluralityof second layers 206 are deposited at a sufficiently low temperature,for example between about 300 degrees Celsius to about 750 degreesCelsius, to prevent intermixing of the different atomic species. As aresult, interfaces between the different atomic species may becontrolled which provides advantageous control of the structure duringselective etching or modification processes, such as oxidationprocesses.

The material layers of the superlattice structure 200 may havecontrolled thicknesses to provide for substantially defect freecrystallographic profiles of the various materials. In one embodiments,the layers of the superlattice structure 200 have a thickness of betweenabout 3 nm and about 50 nm. For example, the plurality of first layers204 have a thickness 220 between about 3 nm and about 10 nm, such asbetween about 5 nm and 7 nm, for example, about 6 nm. The plurality ofsecond layers 206 have a thickness 218 of between about 5 nm and about15 nm, such as between about 7 nm and about 10 nm, for example, about 8nm. The material layer 210 has a thickness 214 of between about 5 nm andabout 15 nm, such as between about 8 nm and about 12 nm, for example,about 10 nm. The material layer 208 has a thickness 216 if between about5 nm and about 15 nm, such as between about 8 nm and about 12 nm, forexample, about 10 nm.

During formation of the superlattice structure 200 on the substrate 202,the various material layers are deposited in certain sequences tomanufacture one or more devices within the superlattice structure 200.In one embodiment, the material layer 210 is disposed on the substrate202 and the material layer 208 is disposed on the material layer 210. Inanother embodiment, the material layer 210 may be optional, such thatthe material layer 208 is disposed on the substrate 202.

The plurality of second layers 206 and the plurality of first layers 204are deposited in an alternating arrangement to form a stacked structure.In this embodiment, one of the second layers 206 is disposed on thematerial layer 208 and one of the first layers 204 is disposed on theone of the second layers 206. A hardmask layer 212 may also be disposedon the superlattice structure 200. In one embodiment, the hardmask layer212 is disposed on one of the first layers 204. The hardmask layer 212may be any suitable hardmask material, such as a silicon nitridematerial or the like.

FIG. 3 illustrates a schematic, cross-sectional view of a portion of thesubstrate 202 and superlattice structure 200 of FIG. 2 after patterning,etching, and oxidation processes are performed. In one embodiment,photolithography processes, such as extreme ultraviolet patterningprocesses, is utilized to pattern the substrate 202 and the superlatticestructure 200. In another embodiment, self-aligned double or quadruplepatterning processes is utilized to pattern the substrate 202 and thesuperlattice structure 200. The patterning processes may be configuredto enable formation of the superlattice structure 200 after an etchingprocess with a channel width 302 of between about 5 nm and about 15 nm,for example, between about 7 nm and about 10 nm.

Exemplary etching processes which may be utilized to etch the substrate202 and the superlattice structure 200 reactive ion etching (RIE)processes or the like. In one embodiment, an RIE process is performedutilizing a chlorine, bromine, or fluorine based chemistry toanisotropically etch the substrate 202 and the superlattice structure200.

The superlattice structure 200 formed on the substrate 202 is alsosubjected to an oxidation process. The oxidation process selectivelyoxidizes one or more of the various material layers of the superlatticestructure 200. Suitable oxidation processes include decoupled plasmaoxidation processes, remote plasma oxidation processes, ultravioletozone oxidation processes, and radical oxidation processes. For example,the oxidation process selectively oxidizes the material layer 208. Theoxidation process may be configured such that the relatively lowgermanium content layers, for example, the material layer 210 and theplurality of second layers 206, are not oxidized during the oxidationprocess while providing for oxidation of relatively high germaniumcontent layers, such as the material layer 208. After selectiveoxidation, the material layer 208 is transformed into a buried oxide(BOX) layer 308. In one embodiment, oxidation of the material layer 208to form the BOX layer 308 also includes oxidation of the material layer210 as a result of the material layer's proximity to the material layer208. However, in this embodiment, the plurality of second layers 206remain substantially unoxidized.

In one embodiment, a radical oxidation process is utilized to form theBOX layer 308. The radical oxidation process generally exposes a desiredmaterial to oxygen radicals to selectively oxidize a desired materiallayer. The substrate 202 and superlattice structure 200 are disposed ina processing environment configured for performing a radical oxidationprocess. A temperature of the radical oxidation process is between about500° C. and about 900° C., such as between about 600° C. and about 800°C., for example, about 700° C. The radical oxidation process isperformed at a pressure of between about 1 milliTorr and about 760 Torr,such as between about 1 Torr and about 100 Torr, for example, about 7Torr. The radical oxidation process may be performed for an amount oftime sufficient to oxidize the high germanium content material layers.In one embodiment, the radical oxidation process is performed for anamount of time between about 1 second and about 60 seconds, such asbetween about 10 seconds and about 30 seconds, for example, about 20seconds.

Precursors provided to the processing environment during the radicaloxidation process include oxygen containing precursors and hydrogencontaining precursors. In one embodiment, O₂ and H₂ are utilized in aratio of between about 50:1 (O₂: H₂) to about 150:1, such as betweenabout 90:1 and about 110:1, for example, about 100:1. In thisembodiment, O₂ is provided at a flow rate of between about 10 slm andabout 100 slm, such as between about 15 slm and about 30 slm, forexample about between about 19 slm and about 20 slm. H₂ is provided at aflow rate of between about 0.1 slm, and about 1.0 slm, such as about 0.2slm. In the aforementioned embodiments, the processing environment isconfigured for performing radical oxidation processes on 300 mmsubstrates.

Utilizing a radical oxidation process according to the aforementionedembodiments oxidizes approximately 1 nm of material per second. Forexample, if the material layer 208 has a channel width 302 of about 40nm, the oxidation process is performed for about 20 seconds. It isbelieved that oxidation of the material layer 208 proceeds fromsidewalls of the material layer 208 inward. Therefore, the oxidationtime (t) to form the BOX layer 308 (utilizing suitable processingparameters) may generally be defined as t=n/2, where n is the channelwidth 302. By performing selective oxidation to form the BOX layer 308prior to subsequent processing operations, efficiencies in processingmay be realized. For example, the amount of time utilized to fullyoxidize the BOX layer 308 may be reduced. Moreover, improved oxidationselectivity may be realized as there are fewer materials and structuresto select from when compared to oxidation processes performed duringsubsequent processing operations. In addition, the BOX layer formationprocess may be performed without capping layers required in variousconventional processes.

FIG. 4 illustrates a schematic, cross-sectional view of a portion of thesubstrate 202 and superlattice structure 200 of FIG. 3 after a linerformation process is performed. During the previously described etchingprocess, sidewalls of the superlattice structure 200 may be damaged. Aliner deposition process is performed to deposit a liner material 402 onsidewalls of the superlattice structure 200 and at least a portion ofthe substrate 202.

The liner material deposition process includes several distinctoperations to manufacture the liner material 402. For example, a thermaloxidation process is performed to deposit an oxide material on sidewallsof the superlattice structure 200, which includes the BOX layer 308, andthe substrate 202. Subsequently, a nitridation process, such as adecoupled plasma nitridation process, is performed to incorporatenitrogen in the oxide material to form an oxynitride material. Theoxynitride liner material 402 is then subjected to a post-nitridationannealing process to further incorporate the nitrogen into the oxidematerial. The post-nitridation annealing process may also cure defectsthat may exist in the liner material 402.

In one embodiment, a width 404 of the liner material 402 is betweenabout 5 Å and about 50 Å, such as between about 20 Å and about 30 Å, forexample, about 25 Å. It is contemplated that the liner material 402 maybe suitable for preventing oxidation of unoxidized material layers ofthe superlattice structure 200 during a subsequent shallow trenchisolation process.

FIG. 5 illustrates a schematic, cross-sectional view of a portion of thesubstrate 202 and superlattice structure 200 of FIG. 4 after a shallowtrench isolation (STI) process is performed. The STI process isgenerally performed to electrically isolate at least one of thesubstrate 202 and/or the superlattice structure 200 from wells havingdifferent conductivity types (e.g., n-type or p-type) and/or adjacenttransistor features (not shown) on the substrate 202. In one embodiment,the STI process is a flowable CVD deposition process configured todeposit a dielectric material layer 502, such as a silicon oxidematerial or a silicon nitride material. The dielectric material layer502 is formed using a high-density plasma CVD system, a plasma enhancedCVD system, and/or a sub-atmospheric CVD system, among other systems.Examples of CVD systems that may be adapted to form the dielectricmaterial layer 502 include the ULTIMA HDP CVD® system and PRODUCER®ETERNA CVD® system, both available from Applied Materials, Inc., ofSanta Clara, Calif. It is contemplated that other suitably configuredCVD systems from other manufacturers may also be utilized.

FIG. 6 illustrates a schematic, cross-sectional view of a portion of thesubstrate 202 and superlattice structure 200 of FIG. 5 after anannealing process is performed. The annealing process is performed todensify the dielectric material layer 502 to form a densified dielectricmaterial layer 602.

In one embodiment, the annealing process includes a steam annealingprocess. The steam annealing process is performed at a temperature ofbetween about 300 degrees Celsius and about 800 degrees Celsius, such asbetween about 500 degrees Celsius and about 600 degrees Celsius. Thesteam annealing process is performed for an amount of time between about15 minutes and about 180 minutes, for example, about 120 minutes. Thesteam annealing process may also further oxidize the densifieddielectric material layer 602.

In another embodiment, the annealing process also includes a dryannealing process. The dry annealing process is performed at atemperature of between about 500 degrees Celsius and about 1000 degreesCelsius, such as between about 650 degrees Celsius and about 750 degreesCelsius. The dry annealing process is performed for an amount of timebetween about 1 minute and about 60 minutes, for example, about 30minutes. In yet another embodiment, both the steam annealing process andthe dry annealing process are utilized together. In this embodiment, thedry annealing process is performed after the steam annealing process.

After the one or more annealing processes are performed, the substrate202 is planarized. More specifically, the densified dielectric materiallayer 602 may be polished, etched, or otherwise modified such that a topsurface of the densified dielectric material layer 602 is substantiallyco-planar with the hardmask layer 212. In one embodiment, the hardmasklayer 212 is utilized as a stop indicator for a chemical mechanicalpolishing process. In one embodiment, the hardmask layer 212 is removedfrom the superlattice structure 200 after planarization of the densifieddielectric material layer 602.

FIG. 7 illustrates a schematic, cross-sectional view of a portion of thesubstrate 202 and superlattice structure 200 of FIG. 6 after an STIrecess process is performed. The STI recess process is generally anetching process configured to remove at least a portion of the densifieddielectric material layer 602. In one embodiment, a top surface 702 ofthe densified dielectric material layer 602 is removed such that the topsurface 702 is substantially co-planar with the BOX layer 308 or with aninterface between the BOX layer 308 at one of the plurality of secondlayers 206. The STI recess process also removes a portion of the linermaterial 402. In one embodiment, the STI recess process is a remoteplasma assisted dry etching process which exposes various materialsdisposed on the substrate 202 to H₂, NF₃, and NH₃ plasma by-products.The STI recess process is generally a conformal removal process and isselective to silicon oxide materials but does not readily etch silicon.For example, the removal rate of the BOX layer 308 may be less than theremoval rate of the densified dielectric material layer 602. Theexistence of the liner material 402 may further reduce or preventetching of the BOX layer 308 during the STI recess process. Accordingly,over etching or undercutting of the BOX layer 308 may be reduced oreliminated during etching of the densified dielectric material layer602. In one embodiment, the STI recess process is performed by a SICONI®process and suitably configured apparatus, available from AppliedMaterials, Inc., Santa Clara, Calif. It is contemplated that othersuitable etching processes and apparatus may also be utilized to performthe STI recess process.

After performing the STI recess process, subsequent hGAA or FinFETprocessing operations may be performed. Advantageously, the BOX layer308 is self-aligned to a bottom region of the superlattice structure200. The self-aligned BOX formation process described hereinadvantageously improves transistor device performance and reducestransistor device variability by reducing or eliminating parasiticcapacitance and leakage. In addition, processing flexibility andefficiency of BOX layer formation may be realized by forming the BOXlayer 308 prior to depositing the dielectric material layer 502 or byforming the BOX layer 308 after deposition of the dielectric materiallayer 502.

Subsequent processing operations for forming hGAA and FinFET devicestructures generally include gate structure formation and source/drainformation. FIG. 8 illustrates a schematic, cross-sectional view of thesubstrate 202 and superlattice structure 200 with a dummy gate structure802 formed thereon. The dummy gate structure 802 is formed from one ormore materials suitable for utilization as a placeholder for subsequentreplacement metal gate formation. In one embodiment, the dummy gatestructure 802 is formed from a silicon containing material, such asamorphous silicon or the like.

FIG. 9 illustrates a schematic, cross-sectional view of FIG. 8 rotated90° along section line 9-9 depicting source/drain regions 902 formed onthe substrate 202 adjacent the superlattice structure 200. Thesource/drain regions 902 are generally deposited on the substrate 202such that the source/drain regions 902 couple with the superlatticestructure 200 (which may function as a channel) and facilitate the flowof electrons and holes therebetween.

The source/drain regions 902 are formed from suitable materials, such assilicon containing materials, doped silicon materials, compound siliconmaterials, or non-silicon containing materials. For example, thesource/drain regions 902 may be silicon, phosphorous doped silicon,silicon germanium materials, or germanium. It is contemplated that thetype of source/drain region material is selected in response to desiredn-type or p-type characteristics of the source/drain regions 902. Thesource/drain regions 902 are deposited by suitable depositiontechniques, such as CVD techniques or epitaxial deposition techniques.

In one embodiment, such as hGAA integration schemes, the plurality ofsecond layers 206 and the dummy gate structure 802 are replaced by ametal gate structure 904. The plurality of second layers 206 and thedummy gate structure 802, which exhibit sufficiently differentcompositional profiles to other layers of the superlattice structure200, are removed by selective etching processes. In certain embodiments,the dummy gate structure 802 is removed by a first etching processselective to the material of the dummy gate structure 802 and theplurality of second layers 206 are removed by a second etching processselective to the material of the second layers 206. Alternatively, thedummy gate structure 802 and the plurality of second layers 206 areremoved by a single etching process. Although not illustrated, incertain embodiments, a spacer material is disposed between thesource/drain regions 902 and the metal gate structure 904. In thisembodiment, deposition of the spacer material is performed prior todeposition of the source/drain regions 902.

Subsequently, the metal gate structure 904 is deposited in regionspreviously occupied by the dummy gate structure 802 and the plurality ofsecond layers 206. Generally, the metal gate structure 904 may bedeposited by suitably configured epitaxial processes, atomic layerdeposition (ALD) processes, or CVD processes. Materials utilized for themetal gate structure 904 generally exhibit a k-value of greater thanabout 3.9. Examples of materials with suitably high k values includehafnium dioxide, zirconium dioxide, titanium dioxide, titanium nitride,and titanium aluminide, among others. Various other nitride materialsare utilized in certain embodiments. In one embodiment, the materialsdescribed above are utilized for portions of the metal gate structure904 which replace the plurality of second layers 206.

A portion of the metal gate structure 904 which replaces the dummy gatestructure 802 is formed from a metal containing material and/or aconductive material. For example, suitable materials include titaniumcontaining materials, such as TiN or TiAIC, and tantalum containingmaterials, such as TaN. Other suitable materials include refractorymetals, such as tungsten, ruthenium, rhenium, and the like. In certainembodiments, materials utilized to form regions of the metal gatestructure 904 which replace the plurality of second layers 206 and thedummy gate structure 802 are the same materials or different materialsas described above. The types of materials selected for the metal gatestructure 904 may be determined by the transistor type (i.e. NMOS/PMOS).

In one embodiment, if the BOX layer 308 has not been previouslyoxidized, an oxidation process is performed during and/or afterformation of the source/drain regions 902. Accordingly, processflexibility in forming the BOX layer 308 is improved which may providefor more efficient BOX layer formation and improved device performance,depending on the desired integration scheme. It is contemplated thathGAA and FinFET processing sequences, among others, can derive benefitsfrom implementing the above described BOX layer formation schemes (i.e.BOX layer 308 formed before deposition of dielectric material layer 502or BOX layer 308 formed after deposition of dielectric material layer502).

FIG. 10 illustrates a schematic, plan view of a cluster tool 1080suitable for performing one or more portions of the present disclosure.Generally, the cluster tool 1080 is a modular system comprising multiplechambers (e.g., process chambers 1090A-D, service chambers 1091A-B, orthe like) which perform various functions, including: substratecenter-finding and orientation, degassing, annealing, deposition and/oretching.

The cluster tool 1080 includes at least a semiconductor substrateprocess chamber configured to perform at least portions of the method100 and may further include chambers such as ion implantation chambers,etch chambers, deposition chambers and the like. The multiple chambersof the cluster tool 1080 are mounted to a central vacuum transferchamber 1088 which houses a robot 1089 adapted to shuttle substratesbetween the chambers. The vacuum transfer chamber 1088 is typicallymaintained at a vacuum condition and provides an intermediate stage forshuttling substrates from one chamber to another and/or to a load lockchamber 1084 positioned at a front end of the cluster tool 1080. Afront-end environment 1083 is shown positioned in selectivecommunication with the load lock chambers 1084. A pod loader 1085disposed in the front-end environment 1083 is capable of linear androtational movement (arrows 1082) to shuttle cassettes of substratesbetween the load lock chambers 1084 and a plurality of pods 1087 whichare mounted on the front-end environment 1083.

The cluster tool 1080 also includes a controller 1081 programmed tocarry out the various processing methods performed in the cluster tool1080. For example, the controller 1081 is configured to control flow ofvarious precursor and process gases from gas sources and controlprocessing parameters associated with material deposition or etchingprocesses. The controller 1081 includes a programmable centralprocessing unit (CPU) 1079 that is operable with a memory 1077 and amass storage device, an input control unit, and a display unit (notshown), such as power supplies, clocks, cache, input/output (I/O)circuits, and the like, coupled to the various components of the clustertool 1080 to facilitate control of the substrate processing. Thecontroller 1081 also includes hardware for monitoring substrateprocessing through sensors in the cluster tool 1080. Other sensors thatmeasure system parameters such as substrate temperature, chamberatmosphere pressure and the like, may also provide information to thecontroller 1081.

To facilitate control of the cluster tool 1080 described above, the CPU1079 may be one of any form of general purpose computer processor thatcan be used in an industrial setting, such as a programmable logiccontroller (PLC), for controlling various chambers and sub-processors.The memory 1077 is coupled to the CPU 1079 and the memory 1077 isnon-transitory and may be one or more of readily available memory suchas random access memory (RAM), read only memory (ROM), floppy diskdrive, hard disk, or any other form of digital storage, local or remote.Support circuits 1075 are coupled to the CPU 1079 for supporting theprocessor in a conventional manner. Deposition, etching, and otherprocesses are generally stored in the memory 1077, typically as asoftware routine. The software routine may also be stored and/orexecuted by a second CPU (not shown) that is remotely located from thehardware being controlled by the CPU 1079.

The memory 1077 is in the form of computer-readable storage media thatcontains instructions, that when executed by the CPU 1079, facilitatesthe operation of the cluster tool 1080. The instructions in the memory1077 are in the form of a program product such as a program thatimplements the method of the present disclosure. The program code mayconform to any one of a number of different programming languages. Inone example, the disclosure is implemented as a program product storedon computer-readable storage media for use with a computer system. Theprogram(s) of the program product define functions of the embodiments(including the methods described herein). Illustrative computer-readablestorage media include, but are not limited to: (i) non-writable storagemedia (e.g., read-only memory devices within a computer such as CD-ROMdisks readable by a CD-ROM drive, flash memory, ROM chips or any type ofsolid-state non-volatile semiconductor memory) on which information ispermanently stored; and (ii) writable storage media (e.g., floppy diskswithin a diskette drive or hard-disk drive or any type of solid-staterandom-access semiconductor memory) on which alterable information isstored. Such computer-readable storage media, when carryingcomputer-readable instructions that direct the functions of the methodsdescribed herein, are embodiments of the present disclosure.

For the purposes of practicing embodiments of the present disclosure, atleast one of the processing chambers (for example, 1090A) of the clustertool 1080 is configured to perform an etch process, a second processingchamber (for example 1090B) is configured to perform a cleaning processand a third processing chamber (for example 1090C) is configured toperform a epitaxial deposition process. A cluster tool having therecited configuration may advantageously prevent unwanted oxidationafter the source/drain recess is etched and reduces or eliminatessubsequent cleaning of oxidized surfaces prior to epitaxial deposition.In some embodiments, at least one of the processing chambers (forexample, 1090A) of the cluster tool 1080 is configured to perform aselective etch process, and a second processing chamber (for example1090B) is configured to perform a deposition process, for example,deposition of a dielectric material. A cluster tool having the recitedconfiguration may advantageously prevent oxidation of the channelstructure upon exposure of the hGAA or FinFET channel.

FIG. 11 schematically illustrates a cross-sectional view of a devicestructure 1100 formed and/or implemented in a device according toembodiments described herein. The device structure 1100 is generallyconsidered an additional embodiment of a superlattice structure asdefined above. In one embodiment, the device structure 1100 is formed onthe substrate 202. In one embodiment, the device structure 1100 includesthe material layer 210 disposed on the substrate 202, the BOX layer 308disposed on the material layer 210, and a single first layer 204disposed on the BOX layer 308. In another embodiment, the devicestructure 1100 includes the BOX layer 308 disposed directly on thesubstrate 202 and the single first layer 204 disposed on the BOX layer308. In this embodiment, the material layer 210 is not present betweenthe substrate 202 and the BOX layer 308.

Materials suitable for forming the single first layer 204 includesilicon containing materials, such as pure silicon and doped siliconmaterials. Other materials suitable for forming the single first layer204 include silicon germanium materials. For example, the silicongermanium materials comprise between about 20% and about 40% germaniumand between about 60% and about 80% silicon. It is contemplated that thedevice structure 1100 may be utilized advantageously in FinFETintegration schemes. In one embodiment, the device structure 1100 isprocessed according to the operations described in FIG. 1 and FIGS. 3-7.The device structure 1100 may also be implemented according to thedisclosure of FIGS. 8-9 without processing operations directed toreplacement of the plurality of second layers 206.

FIG. 12 illustrates a schematic, cross-sectional view of a deviceincorporating the device structure 1100 of FIG. 11. As shown, the devicestructure 1100 may be processed according to the disclosure of FIGS. 8-9as described above to form a device including the source/drain regions902 and the metal gate structure 904. It is contemplated that theembodiments described with regard to FIG. 12 may be advantageouslyimplemented with regard to forming a FinFET type device while theembodiments described with regard to FIG. 9 may be advantageouslyimplemented with regard to forming an hGAA type device. However,embodiments from both FinFET and hGAA schemes may be utilized alone orin combination for form device structures which exhibit improved processflexibility in forming the BOX layer 308 and provide for more efficientBOX layer formation and improved device performance.

While the foregoing is directed to embodiments of the presentdisclosure, other and further embodiments of the disclosure may bedevised without departing from the basic scope thereof, and the scopethereof is determined by the claims that follow.

What is claimed is:
 1. A device structure, comprising: a substratehaving a superlattice structure formed thereon, the superlatticestructure comprising: a silicon material layer; a first silicongermanium material layer comprising between about 20% and about 40%germanium; and a second silicon germanium material layer comprisingbetween about 50% and about 80% germanium, wherein the silicon materiallayer, the first silicon germanium material layer, and the secondsilicon germanium layer are disposed in a stacked arrangement.
 2. Thedevice structure of claim 1, wherein the second silicon germaniummaterial layer is disposed between first silicon germanium materiallayers.
 3. The device structure of claim 2, further comprising: a linerformed on sidewalls of the superlattice structure, wherein the liner isan oxynitride material, a silicon nitride material, or combinationsthereof.
 4. A device structure, comprising: a superlattice structure,comprising: a silicon material layer; a first silicon germanium materiallayer comprising between about 20% and about 40% germanium; and a secondsilicon germanium material layer comprising between about 50% and about80% germanium, wherein the silicon material layer, the first silicongermanium material layer, and the second silicon germanium layer aredisposed in a stacked arrangement.
 5. The device structure of claim 4,wherein the second silicon germanium material layer is disposed betweenthe first silicon germanium material layers.
 6. The device structure ofclaim 5, further comprising: a liner formed on sidewalls of thesuperlattice structure, wherein the liner is an oxynitride material, asilicon nitride material, or combinations thereof.
 7. A devicestructure, comprising: a substrate having a superlattice structureformed thereon, the superlattice structure comprising: one or moresilicon material layers; one or more silicon germanium material layerscomprising between about 20% and about 40% germanium; and a buried oxidelayer, wherein the silicon material layers, the silicon germaniummaterial layers, and the buried oxide layer are disposed in a stackedarrangement.
 8. The device structure of claim 7, wherein the buriedoxide layer is disposed between the silicon germanium material layers inthe stacked arrangement.
 9. The device structure of claim 8, furthercomprising: a liner formed on sidewalls of the superlattice structure,wherein the liner is an oxynitride material, a silicon nitride material,or combinations thereof.
 10. A device structure, comprising: asuperlattice structure, comprising: one or more silicon material layers;one or more silicon germanium material layers comprising between about20% and about 40% germanium; and a buried oxide layer, wherein thesilicon material layers, the silicon germanium material layers, and theburied oxide layer are disposed in a stacked arrangement.
 11. The devicestructure of claim 10, wherein the buried oxide layer is disposedbetween the silicon germanium material layers in the stackedarrangement.
 12. The device structure of claim 11, further comprising: aliner formed on sidewalls of the superlattice structure, wherein theliner is an oxynitride material, a silicon nitride material, orcombinations thereof.
 13. The device structure of claim 10, furthercomprising: a liner formed on sidewalls of the superlattice structure.14. The device structure of claim 13, wherein the liner is an oxynitridematerial, a silicon nitride materials, or combinations thereof.
 15. Adevice structure, comprising: a substrate having a superlatticestructure formed thereon, the superlattice structure comprising: one ormore silicon material layers; one or more silicon germanium materiallayers comprising between about 20% and about 40% germanium; and aburied oxide layer, wherein the silicon material layers, the silicongermanium material layers, and the buried oxide layer are disposed in astacked arrangement; source/drain regions formed on the substrate; and ametal gate structure formed over the superlattice structure.
 16. Thedevice structure of claim 15, wherein the buried oxide layer is disposedbetween the silicon germanium material layers in the stackedarrangement.
 17. The device structure of claim 15, further comprising: aliner formed on sidewalls of the superlattice structure, wherein theliner is an oxynitride material, a silicon nitride material, orcombinations thereof.
 18. A device structure, comprising: a substrate; aburied oxide layer disposed on and in contact with the substrate; asilicon layer or silicon germanium layer comprising between about 20%and about 40% germanium disposed on the buried oxide layer; source/drainregions formed on the substrate; and a metal gate structure formed overthe silicon layer or silicon germanium layer.
 19. The device structureof claim 18, wherein the source/drain regions are formed from a materialselected from the group consisting of silicon, phosphorous dopedsilicon, silicon germanium, germanium, and combinations thereof.
 20. Thedevice structure of claim 18, wherein the metal gate structure is formedfrom a materials selected from the group consisting of hafnium dioxide,zirconium dioxide, titanium dioxide, titanium nitride, titaniumaluminide, nitride materials, and combinations thereof.